Introducing Gen 4 SiC FETs
The new Gen 4 UJ4C series of SiC FETs deliver breakthrough performance levels designed to accelerate the power performance gains in automotive and industrial charging, telecom rectifiers, datacenter PFC DC-DC conversion as well as renewable energy and energy storage applications. Highlights of the new SiC FET series are:
- 750V VDS rating
- Best-in-class performance figures of merit that lower conduction losses and increase efficiency at higher speed, all at new levels of cost effectiveness
- Safely driven with standard 0V to 12V or 15V gate drive voltage
- Excellent threshold noise margin maintained with true 5V threshold voltage
- Operates with all Si IGBT, Si MOSFET and SiC MOSFET drive voltages
- Built-in ESD gate protection clamp
- All devices are AEC-Q101 qualified
- Uses industry-standard TO247-3L and TO247-4L (Kelvin) packages
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Key Features
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750V
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Low RDS(on) from 18mohm to 60mohm
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Key Figures of Merit enable next gen, high-performance power designs
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Best-in-class RDS(on) x Area
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Improve the Qrr and Eon/Eoff losses at a given RDS(on)
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Reduce both Coss(er)/Eoss and Coss(tr)
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Excellent reverse recovery
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Excellent body diode performance (Vf<2V)
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Low gate charge
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ESD protected, HBM class 2
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TO247-3L & TO247-4L (Kelvin) packages
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AEC-Q101 qualified

Product Specifications
Best Figures of Merit
Figure-of-Merit (FoM) comparisons are critical for power designers to assess the performance potential of competing technologies. By evaluating technologies on a FoM basis, designers are able to identify the best technology for their design, not merely based on a specific product spec, but compare performance widely across a variety of topologies, power levels etc.
UnitedSiC’s new 750V Gen 4 SiC FETs achieve industry-leading performance for power switch FoMs with new benchmarks in RDS(on) x Area, RDS(on) x Coss,tr and RDS(on) x Eoss. The datasheet results shown below illustrate how the new high-performance Gen 4 series devices deliver lower conduction loss, simple gate driving, and reduced switching losses in hard and soft-switched circuits compared to competing SiC FET devices.
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RDS(on) x Area
Lowest conduction losses across useful temperature range, for a given footprint or package type
- 65-75% less conduction losses @ 25°C
- 45-70% less conduction losses @ 125°C


Hard-Switching
Lowest total losses based on low Eoss / Qoss x RDS(on)
- Nearly 2X better than competition
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Soft-Switching
Maintaining low RDS(on) x Coss,tr enables higher power density in soft-switched applications
- 5-10X lower gate drive losses by Qg x VDrive
- Excellent body diode enables reliable operation out of resonance